In order to extend CMOS scaling, dielectrics of higher dielectric constant (Hi-K) are being investigated. For a given gate capacitance, hence charge in the channel, the Hi-K dielectric can be thicker, thus reducing tunneling leakage. To increase the gate capacitance even further, and to have a suitable work-function for thin-silicon implementation, a metal gate is desirable. These material options are frequently incompatible with conventional high-temperature front end of the line processing, so that replacement gate methods are being tried where the Hi-K dielectric and the metal are deposited in a groove formed by removing a dummy gate.
As the gate length of a field effect transistor (FET) gets shorter, the Hi-K dielectric occupies an increasing fraction of the groove. The gate itself tends to be rounded at the bottom, and as a result, only the center of the gate has full control of the channel. Furthermore, the presence of a gap between the Source/Drain (S/D) extension implant regions and the gate edge increases the on-resistance of the FET. Therefore, there is a need for alternate methods of forming a device with better overlap or alignment between the gate and S/D extensions as well as gate contact profile for improved device performance.